1. Field
Device structures.
2. Background
Transistors and other devices are connected together to form circuits, such as very large scale integrated circuits, ultra-large scale integrated circuits, memory, and other types of circuits. When the size of transistors, for example, is reduced and device compaction is increased, problems may arise concerning parasitic capacitance, off-state leakage, power consumption, and other characteristics of a device. Semiconductor on insulator (SOI) structures have been proposed in an attempt to overcome some of these problems. However, SOI structures generally have a high rate of defects, as it is difficult to produce thin, uniform semiconductor layers in fabrication. Defect problems in SOI structures include defects within a single wafer (e.g., the thickness of a wafer differs at various points on the wafer) and defects from wafer to wafer (e.g., an inconsistent mean silicon layer thickness among SOI wafers). As transistor devices are made smaller, channel length is generally reduced. Reduction in the channel length generally results in an increased device speed, as gate delay typically decreases. However, a number of side effects may arise when channel length is reduced. Such negative side effects may include, among others, increased off-state leakage current due to threshold voltage roll-off (e.g., short channel effects).
One way of increasing device speed is to use higher carrier mobility semiconductor materials to form the channel. Carrier mobility is generally a measure of the velocity at which carriers flow in a semiconductor material under an external unit electric field. In a transistor device, carrier mobility is a measure of the velocity at which carriers (e.g., electrons and holes) flow through or across a device channel in an inversion layer. For example, higher carrier mobility has been found in narrow bandgap materials that include germanium (Ge). Germanium has electron and hole mobility of 3900 square centimeters per volt-seconds (cm2/Vsec) and 1900 cm2/Vsec, respectively, which are higher than that of electron and hole mobility of silicon, which are 1500 cm 2/Vsec and 450 cm2/Vsec, respectively. The bandgap associated with a semiconductor material is generally based on the difference between the conduction band edge and valence band edge. Generally, higher mobility semiconductor materials have a narrower bandgap. With germanium, for example, the bandgap is approximately 0.67 electron-volts (eV), which is relatively small compared to that of silicon, which is approximately 1.1 eV.
For 300 millimeters (mm) wafers, it is difficult to grow a single crystal of high carrier mobility material. One way to use higher carrier mobility semiconductor materials in 300 mm or larger wafer size device fabrication is to grow the material epitaxially on a 300 mm or larger silicon carrier wafer. However, there is generally a large lattice mismatch between the high carrier mobility material and silicon. This large lattice mismatch tends to results in a high level of defects in the as grown epitaxial high mobility layer. One technique to reduce the defect density in the epitaxial layer is to introduce a graded buffer layer between the silicon carrier and the high carrier mobility material. By utilizing a graded buffer layer, the lattice parameter is varied in the buffer layer to serve as a transition between, for example, the silicon carrier to the higher carrier mobility epitaxial layer in a gradual fashion from the silicon material with a small or lower lattice mismatch being at the silicon interface and throughout the buffer layer. However, even though this graded buffer layer will tend to reduce some of the defects due to lattice mismatch, it is generally not sufficient to produce acceptable quality epitaxial layers for device applications.